1. Field of the Invention
The invention relates generally to logic circuits and, more particularly, to logic circuits with mixed scan and non-scan memory elements.
2. Description of the Related Art
One purpose of a logic circuit simulator is to allow for verification of a logic circuit's functions so that errors in the logic circuit design can be found and addressed prior to manufacturing. Verification in this context refers to the entire process of testing, debugging, and verifying that the logic circuit behaves as intended.
For verification purposes, it is often desirable to be able to examine the contents of memory elements. For this purpose, memory elements may be connected sequentially, to keep the number of wires manageable, using a separate set of connections known as the scan path. Scan control signals are sent to the memory elements to toggle the input of the memory elements between the scan path and the function path, which is used during the normal operation of the device. During verification for example, the circuit clock can be temporarily suspended, and scan memory elements toggled from the function path to the scan path, allowing the values of the scan memory elements to be scanned out to a host device for analysis.
In prior art logic circuits all memory elements were scanned. However, the number of memory elements in modern designs often outnumber the amount of manageable wires, so newer logic circuits use a mix of scan and non-scan memory elements.
It is desirable for all memory elements to be loaded with specific values during events such as a power on reset (POR) so that a known state for the logic circuit is achieved. Typically, for logic circuits with a mix of scan and non-scan memory elements, only the scan memory elements are loaded with specific values. Thus the logic circuit is not in a known state because the values of the non-scan memory elements are unknown.
Therefore, there is a need for efficiently loading a specific set of values into both the scan memory elements and non-scan memory elements of a logic circuit simulator.